ICs used: LM1117, LM2576, LM317T, ST24LC21, TEA5114A, TEA6415, VPC3230D,SDA55XX SDA5550), TPA3002D2, TDA9885/86, TDA1308, PI5V330, GM6015, MST9883, M74HC4052, MC34063, MSP34X0G, DS90C385, NDS8947
20” TFT-LCD TV is a Progressive TV control system based on the µ-controller SDA555X, with built-in deinterlacer and scaler.
TFT TV is a progressive scan flicker free colour television with PC input, driving an WXGA (1366 x 768) panel with 16:9 aspect ratio. The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’. Sound system output is supplying 2x5W (10%THD) speakers. The chassis is equipped with two full SCART’s, one back-AV, one SVHS, one D-Sub 15 (PC) input, one PC stereo audio input and one line out (left and right) and one HP outputs.
IF PART (TDA988X)
The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing. Both devices can be used for TV, VTR, PC and set-top box applications.
MULTI STANDARD SOUND PROCESSOR
The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip.
These TV sound processing ICs include versions for processing the Multichannel Television Sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
AUDIO AMPLIFIER STAGE WITH TPA3002D2
The TPA3002D2 is a 9-W (per channel) efficient,
Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2
can drive stereo speakers as low as 8 Ω. The high efficiency of the TPA3002D2
eliminates the need for external heatsinks when playing music.
POWER
The LM2576
series of regulators are monolithic integrated circuits ideally suited for easy
and convenient design of a step–down switching regulator (buck converter). All
circuits of this series are capable of driving a 3.0A load with excellent line
and load regulation. Two different versions (one having a fixed output voltage
of 3.3 V, and one with 5.0 V) of this IC are used in the regulator board.MICROCONTROLLER
SDA55XXGeneral
Features• Feature
selection via special function register• Simultaneous
reception of TTX, VPS, PDC, and WSS (line 23)• Supply
Voltage 2.5 and 3.3 V• ROM version
is used.External
Crystal and Programmable Clock Speed• Single
external 6MHz crystal, all necessary clocks are generated internally• CPU clock
speed selectable via special function registers.• Normal Mode
33.33 MHz CPU clock, Power Save mode 8.33 MHz
Ports
• One 8-bit I/O-port with open drain output and optional I 2 C Bus emulation support (Port0)
• Two 8-bit multifunction I/O-ports (Port1, Port3)
• One 4-bit port working as digital or analogue inputs for the ADC (Port2)
• One 2-bit I/O port with secondary function (P4.2, 4.3, 4.7)
• One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52)
SERIAL ACCESS CMOS 16K (2048*8) EEPROM ST24C16
The ST24C16 is a 16Kbit electrically erasable programmable memory (EEPROM), organised as 8 blocks of 256*8 bits. The memory is compatible with the I²C standard, two wire serial interface, which uses a bidirectional data bus and serial clock. The memory carries a built-in 4 bit, unique device identification code (1010) corresponding to the I²C bus definition. This is used together with 1 chip enable input (E) so that up to 2*8K devices may be attached to the I²C bus and selected individually.
CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.
SAW FILTERS
K3953M is an IF Filter for Video Applications. The package is SIP5K. Supported standards are B/G, D/K, I, L/L’.
K9656M is an IF Filter for Audio Applications. The package is SIP5K. Supported standards are B/G, D/K, I, L/L’.
LM1117
General Description
The LM1117 is a series of low dropout voltage
regulators with a dropout of 1.2V at 800mA of load current. It has the same
pin-out as National Semiconductor’s industry standard LM317. The LM1117 is
available in an adjustable version, which can set the output voltage from 1.25V
to 13.8V with only two external resistors. In addition, it is also available in
five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current
limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference
to as-sure output voltage accuracy to within ±1%. The LM1117 series is
available in SOT-223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF
tantalum capacitor is required at the output to improve the transient response
and stability.
Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation.
LM2576
General Description
The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step–down switching regulator (buck converter). All circuits of this series are capable of driving a 3.0 A load with excellent line and load regulation. These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output version. These regulators were designed to minimize the number of external components to simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different inductor manufacturers. Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in comparison with popular three–terminal linear regulators, especially with higher input voltages. In many cases, the power dissipated is so low that no heatsink is required or its size could be reduced dramatically.
A standard series of inductors optimized for use with the LM2576 are available from several different manufacturers. This feature greatly simplifies the design of switch–mode power supplies. The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input voltages
and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is included, featuring 80 mA (typical) standby current. The output switch includes cycle–by–cycle current limiting, as well as thermal shutdown for full protection under fault conditions.
• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions
• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line
and Load Conditions
• Guaranteed 3.0 A Output Current
• Wide Input Voltage Range
• Requires Only 4 External Components
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
• Moisture Sensitivity Level (MSL) Equals 1
LM317T
Description
The LM317T is an adjustable 3 terminal positive
voltage regulator capable of supplying in excess of 1.5 amps over an output
range of 1.25 to 37 volts. This voltage regulator is exceptionally easy to use
and requires only two external resistors to set the output voltage. Further, it
employs internal current limiting,thermal shutdown and safe area compensation,
making it essentially blow–out proof. The LM317 serves a wide variety of
applications including local, on card regulation. This device can also be used
to make a programmable output regulator, or by connecting a fixed resistor
between the adjustment and output, the LM317 can be used as a precision current
regulator.
• Output Current in Excess of 1.5 A
• Output Adjustable between 1.2 V and 37 V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting Constant with Temperature
• Output Transistor Safe–Area Compensation
• Floating Operation for High Voltage Applications
• Available in Surface Mount D2PAK, and Standard 3–Lead Transistor Package
• Eliminates Stocking many Fixed Voltages
ST24LC21
Description
The ST24LC21 is a 1K bit electrically erasable
programmable memory (EEPROM), organized by 8 bits. This device can operate in
two modes: Transmit Only mode and I2C bidirectional mode. When powered, the
device is in Transmit Only mode with EEPROM data clocked out from the rising
edge of the signal applied on VCLK. The device will switch to the I2C
bidirectional mode upon the falling edge of the signal applied on SCL pin. The
ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode
(except when the power supply is removed). The device operates with a power
supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small
Outline packages are available.
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V to 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I2C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances
TEA5114A
General description
This integrated circuit provides RGB switching
allowing connections between peri TV plug, internal RGB generator and video
processor in a TV set.
The input signal black level is tied to the same reference voltage on each
input in order to have no differential voltage when switching two RGB
generators. An AC output signal higher than 2 Vpp makes gain going slowly down
to 0dBto protect the TV set video amplifier from saturation.
Fast blanking output is a logical OR between FB1 (Pin 8) and FB2 (Pin 10).
Features
• 25MHz Bandwidth
• Crosstalk : 55dB
• Short circuit to ground or VCC protected
• Anti saturation gain changing
• Video switching.
TEA6415
General description
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external resistor bridge). All the switching possibilities are changed through the BUS. Driving 75Ω load needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration.
Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor
bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
Pinning
1. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
2. Data : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
3. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
4. Clock : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
5. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
6. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
7. Prog
8. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
9. Vcc : 12V
10. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
11. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
12. Ground
13. Output : 5.5Vpp, Min : 4.5Vpp
14. Output : 5.5Vpp, Min : 4.5Vpp
15. Output : 5.5Vpp, Min : 4.5Vpp
16. Output : 5.5Vpp, Min : 4.5Vpp
17. Output : 5.5Vpp, Min : 4.5Vpp
18. Output : 5.5Vpp, Min : 4.5Vpp
19. Ground
20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
VPC3230D
General Description
The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party products.
The main features of the VPC 323xD are
• high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
• multi-standard colour decoder PAL/NTSC/SECAM including all substandards
• four CVBS, one S-VHS input, one CVBS output
• two RGB/YCr Cb component inputs, one Fast Blank (FB) input
• integrated high-quality A/D converters and associated clamp and AGC circuits
• multi-standard sync processing
• linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panorama-vision’
• PAL+ preprocessing
• line-locked clock, data and sync, or 656-output interface
• peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS
• high-quality soft mixer controlled by Fast Blank
• PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution
• 15 predefined PIP display configurations and expert mode (fully programmable)
• control interface for external field memory
• I2C-bus interface
• one 20.25-MHz crystal, few external components
• 80-pin PQFP package
Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
SUPPLY A = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V
General description
The SDA55XX is a single chip teletext decoder for decoding
World System Teletext data as well as Video Programming System (VPS), Program
Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for PAL plus
transmissions (Line 23). The device also supports Closed caption acquisition
and decoding. The device provides an integrated general-purpose, fully
8051-compatible Microcontroller with television specific hardware features.
Microcontroller has been enhanced to provide powerful features such as memory
banking, data pointers, and additional interrupts etc. The on-chip display unit
for displaying Level 1.5 teletext data can also be used for customer defined on
screen displays. Internal XRAM consists of up to16 Kbytes. Device has an
internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of
external RAM and ROM. The SDA 55XX supports a wide range of standards including
PAL, NTSC and contains a digital slicer for VPS, WSS, PDC, TTX and Closed
Caption, an accelerating acquisition hardware module, a display generator for
Level 1.5 TTX data and powerful On screen Display capabilities based on
parallel attributes, and Pixel oriented characters (DRCS). The 8-bit Microcontroller runs at 360 ns.
cycle time (min.). Controller with dedicated hardware does most of the internal
TTX acquisition processing, transfers data to/from external memory interface
and receives/transmits data via I2C-firmware user-interface. The slicer
combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kilobyte.
The Microcontroller firmware performs all the acquisition tasks (hamming and
parity-checks, page search and evaluation of header control bits) once per
field. Additionally, the firmware can provide high-end Teletext features like
Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is
optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology
with 2.5 V supply voltage and 3.3 V I/O (TTL compatible). The software and
hardware
development environment (TEAM) is available to simplify and speed up the
development of the software and On Screen Display. TEAM stands for TVT Expert
Application Maker. It improves the TV controller software quality in following
aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know
how.
– Modular and open tool chain, configurable by customer
General Description
The TDA1308 is an integrated class AB stereo headphone
driver contained in an SO8 or a DIP8 plastic package. The device is fabricated
in a 1 mm CMOS process and has been primarily developed for portable digital
audio applications.
Features
• Wide temperature range
• No switch ON/OFF clicks
• Excellent power supply ripple rejection
• Low power consumption
• Short-circuit resistant
• High performance
• high signal-to-noise ratio
• High slew rate
• Low distortion
• Large output voltage swing.
General description
The Genesis Microchip 6015RD1 LCD TV reference board is a
complete display processor for LCD, PDP and LCOS based televisions. The
reference board demonstrates the processing capabilities of the Genesis Microchip
gm6015 television controller IC. The gm6015 IC is a full-featured, dual-channel
video processor with Genesis industry leading Crystal Ciema PlusTM video scan
conversion. The 6015RD1 board inputs analog YPbPr/RGB, NTSC/PAL/SECAM CVBS/YC,
UHF/VHF and outputs digital RGB to an XGA LCD panel. A convenient on-screen
display system provides easy control of the board’s processing capabilities.
The design kit is complete with hardware and software. Software includes
G-Probe debug software, GWizard register calculator and G-TV application source
code.
The 6015RD1 is a related reference board that outputs analog YpbPr/RGB.
Features
• Dual channel, gm6015 based LCD TV system
• Industry leading Crystal Cinema Plus video scan conversion
• Inputs:
i. Component analog YPbPr/RGB
ii. 480/576I, 480/576P, 720P and 1080I HD
iii. Dual NTSC/PAL/SECAM CVBS and YC
iv. VGA, SVGA, XGA PC graphics
v. Separate, composite or sync on Y/G
vi. UHF/VHF RF (NTSC)
• Default output with XGA LCD interface PCB:
i. Component analog YpbPr/RGB
• Other outputs:
ii. 8/16/20/24-bit 4:2:2/4:4:4 digital YCbCr/RGB
iii. 480/576I, 480/576P, 720P and 1080I HD
iv. VGA, SVGA, XGA PC graphics
v. Separate, composite or sync on Y/G
• On-screen display (OSD) user interface with automated self running
demonstration
• Small form factor PCB
General Description
The MST9883C is a fully integrated analog interface for
digitizing high-resolution RGB graphics signals from PC’s and workstations.
With a sampling rate capability of up to 140 MHz, it can accurately support display
resolutions up to 1280x1024 (SXGA) at 75 Hz. The clamped input circuits provide
sufficient bandwidth to accurately digitize each pixel.
• Triple ADC with 12 - 140 MHz Sampling Rate
• Integrated line locked PLL generates pixel clock from HSYNC
• Integrated clamp with timing generator
• Integrated Brightness & Contrast controls
• Pin Compatible with AD9883A
• 4:2:2 and 4:4:4 Output Format Mode
• BT656 output format mode*
• Black and mid-level precision clamp and calibration
General description
The M74HC4052 is a dual four-channel analog
MULTIPLEXER/DEMULTIPLEXER fabricated with silicon gate C2MOS technology and it
is pinto pin compatible with the equivalent metal gate CMOS4000B series. It
contains 8 bidirectional and digitally controlled analog switches. A built-in level shifting is included to
allow an input range up to 6V (peak) for an analog signal with digital control
signal of 0 to 6V.
VEE supply pin is provided for analog input signals. It has an inhibit (INH)
input terminal to disable all the switches when high. For operation as a
digital multiplexer/demultiplexer, VEE is connected to GND. A and B control inputs select one channel out
of four in each section.
All inputs are equipped with protection circuits against static discharge and
transient excess voltage.
Features
• Operation from 3.0 V to 40 V Input
• Low Standby Current
• Current Limiting
• Output Switch Current to 1.5 A
• Output Voltage Adjustable
• Frequency Operation to 100 kHz
• Precision 2% Reference
MSP34X0G
MSP3400G
Multistandard Sound Processor Family
Introduction
The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure shows a simplified functional block diagram of the MSP 34x0G.
This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments.
All MSP 34x0G versions are pin and software downward compatible to the MSP 34x0D. The MSP 34x0G further simplifies controlling software. Standard selection requires a single I²C transmission only.
The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I²C interaction is necessary (Automatic Sound Selection)
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line,
2*16 bits) per sampling cycle
(32 kHz) are transmitted.
2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz)
are transmitted.
3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024
MHz).
4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
Features
• Standard Selection with single I2C transmission
• Automatic Standard Detection of terrestrial TV standards
• Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS,
STATUS
• Two selectable sound IF (SIF) inputs
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass
filter
• Spatial effect for loudspeaker channel
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Dolby Pro Logic with DPL 351xA coprocessor
• All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard
• Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
• Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA
specification)
• ASTRA Digital Radio (ADR) together with DRP 3510A
• All NICAM standards
• Korean FM-Stereo A2 standard.
DS90C385
General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44% reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
• 20 to 85 MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130 mW (typ) @85MHz Grayscale
• Tx Power-down mode <200µW (max)
• Supports VGA, SVGA, XGA and Single/Dual Pixel SXGA
• Narrow bus reduces cable size and cost
• Up to 2.38 Gbps throughput
• Up to 297.5 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
NDS8947
General Description
These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
Features
• -4A, -30V. RDS(ON) = 0.065W @ VGS = -10V
RDS(ON) = 0.1W @ VGS = -4.5V.
• High density cell design for extremely low RDS(ON).
• High power and current handling capability in a widely used surface mount package.
• Dual MOSFET in surface mount package.
Microcontroller Features
• 8bit 8051 instruction set compatible CPU.
• 33.33-MHz internal clock (max.)
• 0.360 ms (min.) instruction cycle
• Two 16-bit timers
• Watchdog timer
• Capture compare timer for infrared remote control decoding
• Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit)
• ADC (4 channels, 8 bit)
• UART (rxd, txd)
Memory
• Up to 128 Kilobyte on Chip Program ROM
• Eight 16-bit data pointer registers (DPTR)
• 256-bytes on-chip Processor Internal RAM (IRAM)
• 128bytes extended stack memory.
• Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX
• UP to 16KByte on Chip Extended RAM (XRAM) consisting of;
- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX)
- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software
- 3-Kilobyte Display Memory
Display Features
• ROM Character set supports all East and West European Languages in single device
• Mosaic Graphic Character Set
• Parallel Display Attributes
• Single/Double Width/Height of Characters
• Variable Flash Rate
• Programmable Screen Size (25 Rows x 33...64 Columns)
• Flexible Character Matrixes (HxV) 12 x 9...16
• Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable Characters
in Enhanced Mode
• CLUT with up to 4096 colour combinations
• Up to 16 Colours per DRCS Character
• One out of 8 Colours for Foreground and Background Colours for 1-bit DRCS and ROM Characters.
ROM Characters
• Shadowing
• Contrast Reduction
• Pixel by Pixel Shiftable Cursor With up to 4 Different Colours
• Support of Progressive Scan and 100 Hz.
• 3 X 4Bits RGB-DACs On-Chip
• Free Programmable Pixel Clock from 10 MHz to 32MHz
• Pixel Clock Independent from CPU Clock
• Multinorm H/V-Display Synchronisation in Master or Slave Mode
Acquisition Features
• Multistandard Digital Data Slicer
• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+)
• Four Different Framing Codes Available
• Data Caption only limited by available Memory
• Programmable VBI-buffer
• Full Channel Data Slicing Supported
• Fully Digital Signal Processing
• Noise Measurement and Controlled Noise Compensation
• Attenuation Measurement and Compensation
• Group Delay Measurement and Compensation
• Exact Decoding of Echo Disturbed Signals
SDA55XX (SDA5550)
TPA3002D2
General Description
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as 8 Ω. The high efficiency of the TPA3002D2 eliminates the need for external heatsinks when playing music.
Features
• 9-W/Ch Into an 8-Ω Load From 12-V Supply
• Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements
• 32-Step DC Volume Control From -40 dB to 36 dB
• Line Outputs For External Headphone Amplifier With Volume Control
• Regulated 5-V Supply Output for Powering TPA6110A2
• Space-Saving, Thermally-Enhanced PowerPADTM Packaging
• Thermal and Short-Circuit Protection.
TDA9885/86
General description
The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation including sound AM and FM processing. Both devices can be used for TV, VTR, PC and set-top box applications.
Features
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC bits via I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD).
TDA1308
PI5V330
General description
Pericom Semiconductor’s PI5V series of mixed signal video circuits are produced in the Company’s advanced CMOS low-power technology, achieving industry leading performance. The PI5V330 is a true bidirectional Quad 2-channel multiplexer/demultiplexer that is recommended for both
RGB and composite video switching applications. The VideoSwitch™ can be driven from a current output RAMDAC or voltage output composite video source.
Low ON-resistance and wide bandwidth make it ideal for video and other applications. Also this device has exceptionally high current capability which is far greater than most analog switches offered today. A single 5V supply is all that is required for operation. The PI5V330 offers a high-performance, low-cost solution to switch between video sources. The application section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.
Features
• High-performance, low-cost solution to switch between video sources
• Wide bandwidth: 200 MHz
• Low ON-resistance: 3W
• Low crosstalk at 10 MHz: –58 dB
• Ultra-low quiescent power (0.1 µA typical)
• Single supply operation: +5.0V
• Fast switching: 10 ns
• High-current output: 100 mA
• Packages available:
– 16-pin 300-mil wide plastic SOIC (S)
– 16-pin 150-mil wide plastic SOIC (W)
– 16-pin 150-mil wide plastic QSOP (Q)
GM6015
MST9883
M74HC4052
features
• low power dissipation:
icc = 4µa (max.) at ta=25°c.
• logic level translation to enable 5v logic signal to communicate with ±5v
analog signal
• low "on" resistance:
70Ω typ. (vcc - vee = 4.5v)
50Ω typ. (vcc - vee = 9v)
• wide analog input voltage range: ±6v
• fast switching: tpd = 15ns (typ.) at ta = 25 °c
• low crosstalk between switches
• high on/off output voltage ratio
• wide operating supply voltage range (vcc - vee) = 2v to 12v
• low sine wave distortion: 0.02% at vcc - vee = 9v
• high noise immunity: vnih = vnil = 28 % vcc (min.)
MC34063
Description
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to–DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in Step–Down and Step–Up and Voltage–Inverting applications with a minimum number of external components.
Source Select
• 5-band graphic equalizer for
loudspeaker channel
