HTC-S-01T DVD HOME THEATER SYSTEM - Akai - SMPS - Main and Audio Output schematic
Power
supply AC 230V ~ 50Hz
Power consumption 5022 W
Signal system Standard PAL
Laser Semiconductor laser, wavelength 650/780nm
Power consumption 5022 W
Signal system Standard PAL
Laser Semiconductor laser, wavelength 650/780nm
SPEAKERS
SECTION
Speakers (Front/Center/Rear)
Speaker system Bass reflex
Speaker unit 70 mm dia. cone type
Rated impedance 8 ohms
SUB-WOOFER
SECTIONSpeakers (Front/Center/Rear)
Speaker system Bass reflex
Speaker unit 70 mm dia. cone type
Rated impedance 8 ohms
Speaker system Bass reflex
Speaker unit 180 mm dia. cone type
Rated impedance 4 ohms.
Speaker unit 180 mm dia. cone type
Rated impedance 4 ohms.
SMPS schematic
Main
Audio output Amp:
Circuit descriptions
System
Controller
MT1379 uses an embedded Turbo-8032 as System Controller and provide ICE interface to increase the feasibility of F/W development. Also, MT1379 includes an build-in internal 373 to latch lower byte address from 8032 Port 0 and provide a glue-logic free solution. MT1379 supports up to 1M X 16 bits Flash ROM to store 8032 code, H/W related data, User data, etc. F/W upgrade can be achieved either by debug interface or by disk.
MT1379 uses an embedded Turbo-8032 as System Controller and provide ICE interface to increase the feasibility of F/W development. Also, MT1379 includes an build-in internal 373 to latch lower byte address from 8032 Port 0 and provide a glue-logic free solution. MT1379 supports up to 1M X 16 bits Flash ROM to store 8032 code, H/W related data, User data, etc. F/W upgrade can be achieved either by debug interface or by disk.
Servo
Controller
The servo control is accomplished through the servo DSP (Servo Digital Signal Processor) and its accessory I/O circuits. This servo DSP is capable of performing complex operations and also provides a friendly interface for the system controller. By issuing type 1 and type 2 commands from the system controller, the servo DSP can accomplish various complicated servo control functions, such as tracking, seeking and MT1336/MT1376 chip register programming. As for the servo I/O circuits, it provides interface between the input servo signals and the Servo DSP. It has built-in ADCs to digitize the servo control signal and DACs to provide signals for the actuator and sledge motor. It also has a serial interface to communicate with the MT1336/MT1376 chip.
The servo control is accomplished through the servo DSP (Servo Digital Signal Processor) and its accessory I/O circuits. This servo DSP is capable of performing complex operations and also provides a friendly interface for the system controller. By issuing type 1 and type 2 commands from the system controller, the servo DSP can accomplish various complicated servo control functions, such as tracking, seeking and MT1336/MT1376 chip register programming. As for the servo I/O circuits, it provides interface between the input servo signals and the Servo DSP. It has built-in ADCs to digitize the servo control signal and DACs to provide signals for the actuator and sledge motor. It also has a serial interface to communicate with the MT1336/MT1376 chip.
Analog
Front End
The analog front end contains a data slicer circuit and a data PLL circuit. The RF analog signal from MT1336/MT1376 is quantized by the data slicer to form the EFM/EFM+ bit stream, from which the channel bit clock is extracted by the data PLL.The EFM/EFM+bit stream and bit clock are then output to DPU for channel bit processing.
The analog front end contains a data slicer circuit and a data PLL circuit. The RF analog signal from MT1336/MT1376 is quantized by the data slicer to form the EFM/EFM+ bit stream, from which the channel bit clock is extracted by the data PLL.The EFM/EFM+bit stream and bit clock are then output to DPU for channel bit processing.
DPU
Data path unit (DPU) provides protection on data with lost synchronization patterns and demodulates EFM/EFM+ bit stream into the channel raw data that will be corrected by the decoder. The synchronization protection makes data after the synchronization pattern to be extracted even if the synchronization pattern is not found.
Data path unit (DPU) provides protection on data with lost synchronization patterns and demodulates EFM/EFM+ bit stream into the channel raw data that will be corrected by the decoder. The synchronization protection makes data after the synchronization pattern to be extracted even if the synchronization pattern is not found.
Spindle
Controller
The spindle controller is used to control disc spindle motor. It includes a varipitch CLV clock generator, a CLV/CAV controller, and a PWM generator. The varipitch CLV clock enerator generates a reference clock for the speed of operation. The CLV/CAV controller changes the mode and speed of operation according to servo register setting. The PWM generator generates pulse-width-modulated signal to drive disc spindle motor driver.
The spindle controller is used to control disc spindle motor. It includes a varipitch CLV clock generator, a CLV/CAV controller, and a PWM generator. The varipitch CLV clock enerator generates a reference clock for the speed of operation. The CLV/CAV controller changes the mode and speed of operation according to servo register setting. The PWM generator generates pulse-width-modulated signal to drive disc spindle motor driver.
CSS/CPPM
The CSS/CPPM module provides functions necessary for decoding discs conforming to CSS/CPPM specification.
System Parser.
The system parser is used to help the system controller to decode DVD/SVCD/VCD bit stream just after the channel decoder performing error correction. Acting as a DMA master, it moves bit stream data from RSPC buffer to video, audio, or sub-picture buffer according to system controller request. It also decrypts the scramble data of the CSS/CPPM sectors. Another function of system parser is providing system controller/DSP a DRAM memory copy controller to enhance system controller/DSP performance.
The CSS/CPPM module provides functions necessary for decoding discs conforming to CSS/CPPM specification.
System Parser.
The system parser is used to help the system controller to decode DVD/SVCD/VCD bit stream just after the channel decoder performing error correction. Acting as a DMA master, it moves bit stream data from RSPC buffer to video, audio, or sub-picture buffer according to system controller request. It also decrypts the scramble data of the CSS/CPPM sectors. Another function of system parser is providing system controller/DSP a DRAM memory copy controller to enhance system controller/DSP performance.
Video Decoder
The primary function of MT1379 is to support MPEG1 and MPEG2 video decoding. The video decode engine comprises of variable length decoder (VLD), inverse transformer (IT), motion compensator (MC), and block reconstructor (BR). The video decode engine decodes the variable length encoded symbols in MPEG bit stream and performs inverse scan, inverse quantization, mismatch control and inverse discrete cosine transform onto the variable length decoded data. The motion compensator fetches prediction data from reference picture buffer according to motion vectors and motion prediciton mode for P and B pictures. Finally, the block econstructor combines both the results of inverse transformer and motion compensator to derive the reconstructed image macro block and write back to picture buffer. The video decode engine can also support JPEG and BMP file decoding by common image compression hardware kernels.
Video Output
The Video Output unit contains Video Processor, SPU, OSD, Cursor, TV encoder units, it performs
ƒ Reading decoded video from DRAM buffer
ƒ Scaling the image
ƒ Gamma/Brightness/Hue/Saturation adjustment and edge enhancement
ƒ Reading and decoding SPU and OSD data from DRAM buffer
ƒ Generating hardware cursor image
ƒ Merging the video data, SPU, OSD and cursor
Video Processor
The Video Processor unit controls the transfer of video data stored in the DRAM to an internal or external TV encoder. It uses FIFOs to buffer outgoing luminance and chrominance data, and performs YUV420 to YUV422 conversion and arbitrary vertical/horizontal decimation/interpolation, from 1/4x to 256x. With this arbitrary ratio scaling capability, the Video Processor can perform arbitrary image conversion, such as PAL to NTSC, NTSC to PAL, MPEG1 to MPEG2, Letterbox, Pan-Scan conversion or zoom in, zoom out. It is also capable of interlace to progressive conversion.
The Video Processor unit performs the following functions:
ƒ Requests and receives the decoded picture data from the picture buffer in external DRAM for display ƒ Resample vertical data to create 4:2:2 sample format
ƒ Optionally performs vertical/horizontal re sampling of both luminance and chrominance data
ƒ Performs optional Gamma correction, luminance/chrominance adjustment, and edge enhancement.
The primary function of MT1379 is to support MPEG1 and MPEG2 video decoding. The video decode engine comprises of variable length decoder (VLD), inverse transformer (IT), motion compensator (MC), and block reconstructor (BR). The video decode engine decodes the variable length encoded symbols in MPEG bit stream and performs inverse scan, inverse quantization, mismatch control and inverse discrete cosine transform onto the variable length decoded data. The motion compensator fetches prediction data from reference picture buffer according to motion vectors and motion prediciton mode for P and B pictures. Finally, the block econstructor combines both the results of inverse transformer and motion compensator to derive the reconstructed image macro block and write back to picture buffer. The video decode engine can also support JPEG and BMP file decoding by common image compression hardware kernels.
Video Output
The Video Output unit contains Video Processor, SPU, OSD, Cursor, TV encoder units, it performs
ƒ Reading decoded video from DRAM buffer
ƒ Scaling the image
ƒ Gamma/Brightness/Hue/Saturation adjustment and edge enhancement
ƒ Reading and decoding SPU and OSD data from DRAM buffer
ƒ Generating hardware cursor image
ƒ Merging the video data, SPU, OSD and cursor
Video Processor
The Video Processor unit controls the transfer of video data stored in the DRAM to an internal or external TV encoder. It uses FIFOs to buffer outgoing luminance and chrominance data, and performs YUV420 to YUV422 conversion and arbitrary vertical/horizontal decimation/interpolation, from 1/4x to 256x. With this arbitrary ratio scaling capability, the Video Processor can perform arbitrary image conversion, such as PAL to NTSC, NTSC to PAL, MPEG1 to MPEG2, Letterbox, Pan-Scan conversion or zoom in, zoom out. It is also capable of interlace to progressive conversion.
The Video Processor unit performs the following functions:
ƒ Requests and receives the decoded picture data from the picture buffer in external DRAM for display ƒ Resample vertical data to create 4:2:2 sample format
ƒ Optionally performs vertical/horizontal re sampling of both luminance and chrominance data
ƒ Performs optional Gamma correction, luminance/chrominance adjustment, and edge enhancement.
The Video Processor unit contains two 2-tap vertical filters for luminance and chrominance . These filters are used to interpolate and reposition luminance and chrominance line to improve picture quality. These filters are capble of generating up to eight, unique sub line value between two consecutive scan lines. The generation of lines depends on the ratio between the height of the source image and the target image. In applications where DRAM bandwidth is critical the filters can be configured as simple line-repeating to reduce the DRAM bandwidth required.
The Video Processor unit integrates two separate horizontal post processing filter, a simple 2-tap linear horizontal filter and an 8-tap programmable filter. These filters are provided for scaling images horizontally along the scan line. These two filters is capable of generating up to eight, unique subpixel values between two consecutive pixels on a scan line. The generation of pixels depends on the ratio between the width of the source image and the target image.
SPU
This is a hardware sub-picture decoder. It decodes the compressed SPU image bitstream and CHG_COLCON commands according to SPU header information previously decoded by system controller. The SPU module also allows two SPU objects to be displayed at the same time. SPU image is blended with main video stream.
OSD
The OSD module can operate with 2/4/16/256-color bitmap format (1/2/4/8 bits), and 16/256 color RLC format, all have 16 levels of transparency. In addition, it accepts an special WARP mode, which inserts one programmable RLC code in the bitmap to reduce the image size stored in DRAM. It also features automatic shadow/outline generation in 2-color mode, 2 Highlight areas, 1 Change Color area and 1 OSDVoid area. One OSD area can occupy the full or a partial screen, or multiple OSDs can occur in a screen at the same time, only if they don't occupy the same horizontal line. The output image is blended with the video-SPU mixed stream.
Cursor
A hardware cursor generator is integrated in Video Output Unit. The cursor image is a 32x32 4-color bitmap image, each colors are programmable. Cursor can be enlarged by 2 in both vertical and horizontal directions. Cursor image is multiplexed with video-SPU-OSD mixed stream.
The OSD module can operate with 2/4/16/256-color bitmap format (1/2/4/8 bits), and 16/256 color RLC format, all have 16 levels of transparency. In addition, it accepts an special WARP mode, which inserts one programmable RLC code in the bitmap to reduce the image size stored in DRAM. It also features automatic shadow/outline generation in 2-color mode, 2 Highlight areas, 1 Change Color area and 1 OSDVoid area. One OSD area can occupy the full or a partial screen, or multiple OSDs can occur in a screen at the same time, only if they don't occupy the same horizontal line. The output image is blended with the video-SPU mixed stream.
Cursor
A hardware cursor generator is integrated in Video Output Unit. The cursor image is a 32x32 4-color bitmap image, each colors are programmable. Cursor can be enlarged by 2 in both vertical and horizontal directions. Cursor image is multiplexed with video-SPU-OSD mixed stream.
Audio
Interface
Audio interface consists of Audio Output Interface and Microphone Input Interface.
Audio Output Interface
The MT1379 can support up to 8 channel audio outputs. The output formats can be 16, 24, or 32-bit frames. Left alignment, right alignment, or I2S formats are all supported. With built-in PLL, MT1379 can provide the audio clock (ACLK) for external audio DAC at 384Fs, where Fs is usually 32KHz, 44.1KHz, 48KHz, 96KHz, or 192KHz. ACLK can also be programmed to be from outside MT1379. When ACLK is input to MT1379, the frequency could be 128*n Fs, where n is from 1 to 7.
Audio raw (encoded) data or cooked (decoded) data can be output on a single line using S/PDIF interface. The output slew rate and driving force of this pad are programmable.
Microphone Input Interface
The MT1379 provides a microphone input interface. Two independent microphones’ data could be input to the MT1379. There are two independent digital volume control for these two input channels. The input data formats can also be left alignment, right alignment, or I2S formats.
Audio interface consists of Audio Output Interface and Microphone Input Interface.
Audio Output Interface
The MT1379 can support up to 8 channel audio outputs. The output formats can be 16, 24, or 32-bit frames. Left alignment, right alignment, or I2S formats are all supported. With built-in PLL, MT1379 can provide the audio clock (ACLK) for external audio DAC at 384Fs, where Fs is usually 32KHz, 44.1KHz, 48KHz, 96KHz, or 192KHz. ACLK can also be programmed to be from outside MT1379. When ACLK is input to MT1379, the frequency could be 128*n Fs, where n is from 1 to 7.
Audio raw (encoded) data or cooked (decoded) data can be output on a single line using S/PDIF interface. The output slew rate and driving force of this pad are programmable.
Microphone Input Interface
The MT1379 provides a microphone input interface. Two independent microphones’ data could be input to the MT1379. There are two independent digital volume control for these two input channels. The input data formats can also be left alignment, right alignment, or I2S formats.
