DVD,VCD,CD,CD-R,CD-RW,MP3,PIC-CD,CD+G playback. Video: PAL/AUTO/NTSC
DVD One Board consists of: Loader part that reads and transmits audio and video data saved at Optic Discs (DVD, CD-DA, VCD, CD-R) to MPEG Decoder part; MPEG Decoder part, which, by decoding and encoding data received from the Loader, produces analog signals; and u-Com that controls the overall system including the loader and MPEG decoder.How Does it Operate
Insert the power cord and then power transmitted to each IC, and the SET will be the STANDBY status which requires the least power for input the front panel key, input the STAND BY/ON key, extinguished the LED. Once the Power On key is entered, uCom recognizes it and initiates each chip-set, performs sequential algorithms such as determining whether the disc is in or not, and if in, what type of disc is loaded. Through this process, it can read disc data before transmitting it to the MPEG Decoder. The MPEG Decoder will then decode and encode such data before generating the final analog audio and video signal outputs.
The loader which read the data of audio/video from optic disc and transfer them to MPEG decoder can be divided into Deck total DVD assay(in a short term, Mecha) and Servo. Mecha mounts with the optical pick-up which allows reading the signal of a disc using laser beam and makes it operates and consists of the deck mechanism which allows loading a disc and reading the data. Servo is a sort of circuit which allows operating the loader and recovering the data and consists of Motor Drive IC operating the spindle, the sled, the loading motor.
Motor Drive IC: AT5868S
The AT5868S is a 5-channel BTL driver IC for driving the motors and actuators in products such as CD-ROM/DVD-ROM/DVD-Player drives. Two of the channels use current feedback to minimize the current phase shift caused by the influence of load inductance. Driver IC generates the focus signal and the tracking signal for pick-up actuator, the sled signal for feed, spindle signal and the load signal for opening and closing of the tray. The focus signal, the tracking signal, the sled signal and the spindle signal are input into each relaxant port of the drive IC(in the order of No. 26 pin, 23, 4, and 1) and set the gain amplification and the center voltage through the internal OP-AMP and drive on both sides and then the focus signal and the tracking signal will be output as VOFC+, VOFC- and VOTK+, VOTK- on actuator, the sled signal and the spindle signal will be output as VOSL+, VOSL- and VOLD+, VOLD- on each motor. For the load signal the input opening/closing signal is output as VOTR+, VOTR- through the loading PRE FWD REV circuit.
The AT5868S is a 5-channel BTL driver IC for driving the motors and actuators in products such as CD-ROM/DVD-ROM/DVD-Player drives. Two of the channels use current feedback to minimize the current phase shift caused by the influence of load inductance. Driver IC generates the focus signal and the tracking signal for pick-up actuator, the sled signal for feed, spindle signal and the load signal for opening and closing of the tray. The focus signal, the tracking signal, the sled signal and the spindle signal are input into each relaxant port of the drive IC(in the order of No. 26 pin, 23, 4, and 1) and set the gain amplification and the center voltage through the internal OP-AMP and drive on both sides and then the focus signal and the tracking signal will be output as VOFC+, VOFC- and VOTK+, VOTK- on actuator, the sled signal and the spindle signal will be output as VOSL+, VOSL- and VOLD+, VOLD- on each motor. For the load signal the input opening/closing signal is output as VOTR+, VOTR- through the loading PRE FWD REV circuit.
MPEG Decoder
The signal read from DVD disc is output into the RF signal and Servo related signal through the RF IC and they are input into the MPEG decoder and processed the MPEG decoding and divided into video/audio signal. The video signal is output into the analog audio signal through the built-in encoder block and also the audio signal into the audio DAC through the audio decoder block.
MPEG decoder consists of existing MPEG-2 decoder and single chip combined the digital signal processing part which is the core technology of DVD player with the Servo controller.
DVD Servo And MPEG-2/MPEG-4/DIVX Decoder : ES6698
The ES6698 Vibratto™II processor is a highly integrated single-chip DVD solution that integrates read channel, ECC, Servo DSP, MCU, and MPEG-2/MPEG-4/DivX decoder that has a state-of-the-art 480p/576p progressive-scan video feature to provide brilliant and sharp, flicker-free video output to the display, and with built-in gamma correction and S/PDIF input and output support. The ES6698 performs audio/video stream data processing, TV encoding, Macrovision™ copy protection, DVD system navigation, system control, and housekeeping functions.
The Vibratto-II DVD processor is built on the ESS proprietary dual CPU Programmable Multimedia Processor(PMP) core consisting of 32-bit RISC and 64-bit DSP processors
and offers the best DVD feature set. The processing units enable simultaneous parallel execution of system commands and data processing to perform specialized encoding and decoding tasks. The RISC processor performs bit stream parsing, control audio data output, transfer video and audio data to the vector engine and service system control and housekeeping functions. The vector engine performs audio and video micro-code processing required by A/V standards, such as Dolby Digital®, MPEG and JPEG imaging. These processing tasks include video motion compensation and estimation, loop filtering, Discrete Cosine Transforms(DCT), inverse DCT, quantization, and inverse quantization.
The Vibratto-II DVD processor supports all popular pick-up units, industry standard I²S audio data input and output, EPROM and DRAM access. It also supports both letterbox and pan-and-scan displays, sub-picture overlay, and On-Screen Display(OSD).
The Vibratto-II’s Unified Memory Architecture enables the lowest possible system memory cost by consolidating multiple memory subsystems into a single unit. In addition, the Vibratto-II DVD solution offers support for Karaoke CD+G, DVDAduio, HDCD, CD-DA, Mp3, and WMA. The ES6698 Vibratto-II DVD processor with DTS support is ffered with the ES6698D, which has the same pinout as the standard ES6698. DTS support is provided via software and only works with the ES6698 and ES6698D DVD processors are available in 2 208-pin Plastic Quad Flat Pack(PQFP) device package.
DVD Servo AFE IC : ES6603
The ES6603 is a high-performance, single-chip analog front-end (AFE) device that contains the servo functions, RF attenuator, automatic gain controller (AGC), and programmable equalizer/filter for a DVD player system, and dual auto laser power control circuit to support twin pickups or twin laser systems. The ES6603 incorporates a bi-directional serial port for accessing the programmable functions of the internal AGC, including attenuation and boost/equalization. The DVD servo block of the ES6603 includes mirror detection, defect detection, dual auto laser power control, focus error, center error, and tracking error detection circuits. The ES6603 provides AC-coupled voltage inputs for photo detector signals used to detect center error, focusing error, tracking error, and differential phase tracking error detection for DVD.
The ES6603 also provides an AC-coupled differential or single-ended RF signal input to the programmable attenuator with external AC coupling circuitry, and an ACcoupled single-ended input for RF signals. The attenuator outputs are AC-coupled to the AGC inputs. The AC-coupled DVD and CD inputs are multiplexed in the input stage for accurate error detection. The programmable bandwidth and boost/equalization of the ES6603 is provided by internal 7-bit control DACs, while a variable attenuator is used to program the zero locations. The programmable bandwidth and cutoff range are set by the filter cutoff DAC. Signal equalization with the programmable filter is supported with a wide bandwidth full wave rectifier and a dual rate charge pump. The ES6603 also provides inputs for its internal RF summing mode. These inputs have the gain control amplifiers at the input stage. The gain is controlled by the register bit settings of the serial port. The ES6603 is available in an industry-standard 64-pin low-profile quad flat pack (LQFP) package.
The ES6603 is a high-performance, single-chip analog front-end (AFE) device that contains the servo functions, RF attenuator, automatic gain controller (AGC), and programmable equalizer/filter for a DVD player system, and dual auto laser power control circuit to support twin pickups or twin laser systems. The ES6603 incorporates a bi-directional serial port for accessing the programmable functions of the internal AGC, including attenuation and boost/equalization. The DVD servo block of the ES6603 includes mirror detection, defect detection, dual auto laser power control, focus error, center error, and tracking error detection circuits. The ES6603 provides AC-coupled voltage inputs for photo detector signals used to detect center error, focusing error, tracking error, and differential phase tracking error detection for DVD.
The ES6603 also provides an AC-coupled differential or single-ended RF signal input to the programmable attenuator with external AC coupling circuitry, and an ACcoupled single-ended input for RF signals. The attenuator outputs are AC-coupled to the AGC inputs. The AC-coupled DVD and CD inputs are multiplexed in the input stage for accurate error detection. The programmable bandwidth and boost/equalization of the ES6603 is provided by internal 7-bit control DACs, while a variable attenuator is used to program the zero locations. The programmable bandwidth and cutoff range are set by the filter cutoff DAC. Signal equalization with the programmable filter is supported with a wide bandwidth full wave rectifier and a dual rate charge pump. The ES6603 also provides inputs for its internal RF summing mode. These inputs have the gain control amplifiers at the input stage. The gain is controlled by the register bit settings of the serial port. The ES6603 is available in an industry-standard 64-pin low-profile quad flat pack (LQFP) package.
Flash Memory : A29800UV-70(A29800TV-70/AT49F8192AT/HY29F800ABT-70)
This stores every program required for the operation of DVD player and holds the data of OSD languages and LOGO and send them upon request from u-COM. This allows the update of firmware by CD-R/RW. For DVD module.
Description
The A29800UV-70 is a 5.0 volt only Flash memory organized as 1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The A29800UV-70 offers the RESET function. The 1024 Kbytes of data are further divided into nineteen sectors for flexible sector erase capability. The 8 bits of data appear on I/O0- I/O7 while the addresses are input on A1 to A18; the 16 bits of data appear on I/O0~I/O15. . The A29800UV-70 is offered in 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29800UV-70 can also be programmed in standard EPROM programmers.
This stores every program required for the operation of DVD player and holds the data of OSD languages and LOGO and send them upon request from u-COM. This allows the update of firmware by CD-R/RW. For DVD module.
Description
The A29800UV-70 is a 5.0 volt only Flash memory organized as 1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The A29800UV-70 offers the RESET function. The 1024 Kbytes of data are further divided into nineteen sectors for flexible sector erase capability. The 8 bits of data appear on I/O0- I/O7 while the addresses are input on A1 to A18; the 16 bits of data appear on I/O0~I/O15. . The A29800UV-70 is offered in 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29800UV-70 can also be programmed in standard EPROM programmers.
EEPROM : S524C20D21(HT24LC02)
This stores the information related to setup of DVD menus. This can read and write the optional information such as OSD, voice, language option after function for subtitle etc, the aspect or method of TV display, video option like display function and audio, screen saver, parental function through the I²C transmission method.
Description
The S524C20D21serial EEPROM has a 2,048-bit (256 byte) capacity, supporting the standard I²C™-bus serial interface. It is fabricated using Samsung most advanced CMOS technology. One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524C20D21is its support for fast mode and standard mode.
This stores the information related to setup of DVD menus. This can read and write the optional information such as OSD, voice, language option after function for subtitle etc, the aspect or method of TV display, video option like display function and audio, screen saver, parental function through the I²C transmission method.
Description
The S524C20D21serial EEPROM has a 2,048-bit (256 byte) capacity, supporting the standard I²C™-bus serial interface. It is fabricated using Samsung most advanced CMOS technology. One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524C20D21is its support for fast mode and standard mode.
SMPS circuit diagram and PWB
SDROM : HY57V641620HGT-H(HY57V641620HGT-55)
This sends and receives data with MPEG decoder and performs the video signal processing. Every video signal output from DVD player is once stored in SDRAM and then encoded in MPEG decoder and finally output into the analog signal. SDRAM applied to DVD module has the capacity of 64MBit(1048576 x 16bit x 4Bank), sends and receives data with MPEG decoder by 16 bit.
Description
The Hynix HY57V641620HGT-H is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HGT-H is organized as 4banks of 1,048,576x16.
HY57V641620HGT-H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
This sends and receives data with MPEG decoder and performs the video signal processing. Every video signal output from DVD player is once stored in SDRAM and then encoded in MPEG decoder and finally output into the analog signal. SDRAM applied to DVD module has the capacity of 64MBit(1048576 x 16bit x 4Bank), sends and receives data with MPEG decoder by 16 bit.
Description
The Hynix HY57V641620HGT-H is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HGT-H is organized as 4banks of 1,048,576x16.
HY57V641620HGT-H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
DAC : DA1132
DA1132 is a high performance stereo digital to analog converter for consumer electronics applications such as, VCD/DVD player, DVD-ROM driver, MPEG-2 card, set-top box, and home theaters etc. It accepts input word length of 16, 18, 20, and 24bits and supports audio sampling frequency from 16KHz to 96KHz. In addition. DA1132 provides a range of control features either via 3-wire serial interface ports or hardware pins.
DA1132 is a high performance stereo digital to analog converter for consumer electronics applications such as, VCD/DVD player, DVD-ROM driver, MPEG-2 card, set-top box, and home theaters etc. It accepts input word length of 16, 18, 20, and 24bits and supports audio sampling frequency from 16KHz to 96KHz. In addition. DA1132 provides a range of control features either via 3-wire serial interface ports or hardware pins.
